/**
 ******************************************************************************
 * @file    chip_define.h
 * @author  hyseim software Team
 * @date    18-Aug-2023
 * @brief   This file provides all the headers of the chipdefine functions.
 ******************************************************************************
 * @attention
 *
 * Copyright (c) 2020 Hyseim. Co., Ltd.
 * All rights reserved.
 *
 * This software is licensed under terms that can be found in the LICENSE file
 * in the root directory of this software component.
 * If no LICENSE file comes with this software, it is provided AS-IS.
 *
 ******************************************************************************
 */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __CHIP_DEFINE_H__
#define __CHIP_DEFINE_H__

#ifdef __cplusplus
extern "C" {
#endif

#define reg64           *(unsigned long long volatile *)
#define reg32           *(unsigned int volatile *)
#define reg16           *(unsigned short volatile *)
#define reg8            *(unsigned char volatile *)
#define word64(x,y)    *(unsigned long long volatile *)(x)=y
#define word32(x,y)    *(unsigned int  volatile *)(x)=y
#define short16(x,y)   *(unsigned short volatile *)(x)=y
#define char8(x,y)     *(unsigned char volatile  *)(x)=y

#define access64(x)    *(unsigned long long volatile *)(x)
#define access32(x)    *(unsigned int   volatile *)(x)
#define access16(x)    *(unsigned short volatile *)(x)
#define access8(x)     *(unsigned char  volatile *)(x)

#define poll0(x,y)  while( reg32(x) & y ) ;
#define poll1(x,y)  while( (reg32(x) & y) == y );

#ifndef NETLIST_SIM
    #define DBG_CMD_BASE 0x70008000
#else
    #define DBG_CMD_BASE 0x70008000
#endif

#define PASS  *(unsigned int  volatile *)(DBG_CMD_BASE+0x20)=1
#define GPASS *(unsigned int  volatile *)(DBG_CMD_BASE+0x0)=1
#define FAIL *(unsigned int  volatile *)(DBG_CMD_BASE+0x4)=1
#define STOP *(unsigned int  volatile *)(DBG_CMD_BASE+0x8)=1


//#define udelay(x)   { unsigned xx = x ; while( xx-- ) { asm("mov r0, r0"); } }
//#define udelay(x)   while( x = x-1 );

// ICCM:16KB  
// DCCM:16KB
// EXTRAM:96KB
#define ICCM_BASE            0x00000000
#define ICCM_SIZE            0x00003FFF
#define DCCM_BASE            0x00020000
#define DCCM_SIZE            0x00003FFF
#define PLIC_BASE            0x01000000
#define PLIC_SIZE            0x00FFFFFF
#define CLINT_BASE           0x00060000
#define CLINT_SIZE           0x00001000
#define DEBUG_BASE           0x00040000
#define DEBUG_SIZE           0x0001FFFF

// memory register
#define EFLASH_BASE          0x27000000
#define EFLASH_SIZE          0x000003FF

#define EXTRAM0_BASE         0x40000000
#define EXTRAM0_SIZE         0x0000FFFF
#define EXTRAM1_BASE         0x40010000
#define EXTRAM1_SIZE         0x00007FFF
#define BOOTROM_BASE         0x30000000
#define BOOTROM_SIZE         0x30003FFF


#define ENET_BASE            0x7A010000
#define HSM_BASE             0x7A020000
#define CAN0_BASE            0x73009000
#define CAN1_BASE            0x7300A000
#define CAN2_BASE            0x7300B000

//---------------------------peri0-------------------------------
#define ASSI1_BASE           0x70000000
#define ASSI3_BASE           0x70001000
#define ASSI5_BASE           0x70002000
#define ASSI7_BASE           0x70003000
#define I2S_BASE             0x70006000
#define CRC_BASE             0x70007000


//---------------------------peri1-------------------------------
#define ASSI0_BASE           0x71000000
#define ASSI2_BASE           0x71000800
#define ASSI4_BASE           0x71001000
#define ASSI6_BASE           0x71001800

//---------------------------peri3 -------------------------------
#define SCU_BASE             0x71003000
#define CMT0_BASE            0x71004000
#define CMT1_BASE            0x71005000
#define CRU_BASE             0x71006000
#define GPIOTOP_BASE         0x71007000
#define TRACE_CFG_BASE       0x71008000
#define DMAC_BASE            0x71009000
#define MPU_BASE             0x7100A000
#define EIM_BASE             0x7100B000
#define ERM_BASE             0x7100C000
#define CAN0_TIMER_BASE      0x7100D000
#define CAN1_TIMER_BASE      0x7100D400
#define CAN2_TIMER_BASE      0x7100D800

//---------------------------peri2_ao -------------------------------
#define CRU_AO_BASE          0x72020000
#define SCU_AO_BASE          0x72021000
#define LPUART2_BASE         0x72022000
#define GPIOAO_BASE          0x7202C000
#define RTC_BASE             0x72024000
#define EWM_BASE             0x72025000
#define LPTIMER_BASE         0x72026000
#define LP_INTR_TIMER_BASE   0x72027000
#define LPI2C_BASE           0x72028000
#define LPSPI_BASE           0x72029000
#define WDOG_BASE            0x7202A000
#define CMP_BASE             0x7202B000


//---------------------------motor -------------------------------
//gpio
#define GPIOA_BASE           0xF0000000
#define GPIOB_BASE           0xF0000400
#define GPIOC_BASE           0xF0000800
#define GPIOD_BASE           0xF0000C00
#define GPIOE_BASE           0xF0001000
#define ADC_TOP_BASE         0xF0002000  // ADC_CMP
#define ADC0_BASE            (ADC_TOP_BASE + 0x0100)
#define ADC1_BASE            (ADC_TOP_BASE + 0x0200)
#define TLAU0_BASE           (ADC_TOP_BASE + 0x0500)
#define TLAU1_BASE           (ADC_TOP_BASE + 0x0600)
#define DAC_CMP_BASE         0xF0003000
#define PDB_BASE             0xF0004000
#define PDB0_BASE            (PDB_BASE + 0x400)
#define PDB1_BASE            (PDB_BASE + 0x800)
#define TRIG_MUX_BASE        0xF0005000
#define ATU_BASE             0xF0006000
#define QEI0_BASE            0xF0007000
#define QEI1_BASE            0xF0008000
#define AORAM_BASE           0x72020800
#define AORAM_SIZE           0x00001000

// TODO:   
#define CRG_BASE             CRU_BASE
#define CRG_AO_BASE          0x72020000
#define CFG_AO_BASE          0x72022000

//==========================================================

#ifdef __cplusplus
        }
#endif

#endif //_SPACC_H_





